Power dissipation in integrated circuits increases as chip frequencies and die area increase. Lowering the power supply voltage has mitigated the rapid increase in power dissipation for designs in newer process technologies but at the cost of larger power supply currents. The electronic current supplied by the power supply grid to each standard cell or custom block (such as a memory) on an Integrated Circuit (IC) chip causes a voltage drop in the supply network due the non-zero impedance (resistance, capacitance and inductance). The voltage drop, if large enough, can cause functional failures. However, even smaller voltage drops that are only a fraction of the power supply voltage can cause timing errors, because the reduced supply voltage increases the delay of logic gates. If the increased delays are not accounted for accordingly, the results of chip timing analyses can be erroneous. Further, large electronic currents can cause failures if the peak current exceeds limits set by the material parameters for the power supply wires. Thus, the design process of a digital circuit typically includes an analysis of the power supply network.
For the design of digital circuits (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist, which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist, which is specific to a particular vendor's technology/architecture.
One operation, which is often desirable in this process, is to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as “floor planning.” A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called “blocks,” and then assigns logic to reside in a block. These regions may be rectangular or non-rectangular. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block (which tends to reduce errors in timing estimates), and the placement and routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
Before the placement and routing operation, the timing of signals are typically estimated from parameters such as the fanout of a net and the estimated wire lengths (e.g., obtained from a route estimation). After placement of components on the chip and routing of wires between components, timing analysis (e.g., timing simulation, or static timing analysis) can be performed to accurately determine the signal delays between logic elements. Further, an analysis of the power supply network can be performed based on the detailed design information.
Currently most techniques for power supply voltage drop estimation rely on a static or DC (Direct Current) analysis of the power supply network (the power grid). In a static or DC analysis, an average or DC current, which is assumed to be constant, is used to represent the actual time varying current in the analysis of the power supply network. The voltage drops in the power supply network are calculated using the average or DC representation of the currents drawn by the cells (e.g., logic gates) of the circuitry.
However, the cells of the circuitry draw time-varying currents from the power supply network in performing state switching activities. Thus, such a traditional DC approach has a number of shortcomings. A traditional DC analysis does not provide any transient voltage drop information. The results of a DC approach are not accurate and could not account for many physical effects such as the placement of de-coupling capacitors or the speed of the transitions of the standard cell outputs.
The actual voltage drop in the power supply network can be much worse than that calculated by the DC analysis because many gates can switch simultaneously, requiring a much larger instantaneous current from the power network than the average current assumed in the DC analysis.
The capacitance and inductance of the power supply network have no impact on the DC analysis, since only the resistance matters in a DC analysis. Therefore, the capacitance and inductance of the power supply network cannot be optimized or analyzed using a DC approach, although in reality they can play a critical role in the actual instantaneous voltage drop.
The timing of the transition of the gates has no effect on the DC analysis. However, whether the logic gates switch simultaneously or in different time windows can produce significantly different power supply voltage drops.
Further, techniques to reduce the peak voltage drop such as the placement and sizing of de-coupling capacitors or different chip packages cannot be analyzed by the traditional DC analysis, since these elements cannot be accounted for in a DC analysis.
A transient analysis of the power supply network may be performed through a detailed circuit level simulation (e.g., using SPICE, Simulation Program with Integrated Circuit Emphasis). Such a detailed circuit level simulation requires transistor level models for every cell. The complexity of the transistor level models severely limits the size of the problem that could be solved. Further, such a detailed circuit level analysis requires stimuli at the inputs of the circuit. Furthermore, the detailed circuit level analysis would have to be performed for each input stimulus applied to the circuit to determine the worst case scenario.
Chen and Ling (1997) described a hierarchical approach for power supply noise analysis in “Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design”, Proc. of Design Automation Conference (DAC), 1997. In the approach of Chen and Ling (1997), the simulation results of functional blocks are used to replace the nonlinear devices and capacitive loads with piecewise linear current sources, which mimic the waveforms of the actual circuits. After the equivalent circuit with the piecewise linear current source for each functional block is generated, the equivalent circuit is used to represent the functional block in the analysis of the top level power network. Similarly, Dharchoudhury et al. described a hierarchical approach in “Design and Analysis of Power Distribution Networks in PowerPC™ Microprocessors”, Proc. of Design Automation Conference (DAC), 1998. After simulating the non-linear devices under the perfect supply voltage to measure the currents drawn by the devices, Dharchoudhury et al. (1998) models the non-linear devices as independent time varying current sources, according to the measured currents, for the simulation of the power grid. However, these approaches require detailed transistor level analyses of the functional blocks. Further, these approaches may only be suitable for the circuits that are designed in a hierarchical way with an obvious block structure. Furthermore, the simulation of a function block requires the generation of input vectors that provide stimulus to the cells in the block. It is difficult to generate input vectors for the efficient simulation of a function block while obtaining a reasonable worst-case switching current for the function block.